FIG. 9A shows an illustrative circuit configuration of a clock synchronization circuit which has a BDD (Bi-Directional Delay) circuit, also termed a bidirectional type delay circuit, as a delay circuit. FIG. 9B shows an operation of the circuit shown in FIG. 9A. Referring to FIG. 9A, the clock synchronization circuit is made up by a clock buffer (CLKB) 401 which receives an external clock signal (CLK) and a complementary signal (/CLK) thereof to output an internal clock signal (ICLK), a replica circuit (REP) 402 which receives and delays the internal clock signal (ICLK) to output a delayed signal, a phase selection circuit (PHR) 403 which receives the internal clock signal (ICLK) to output first and second control signals (PHA and PHB) for phase selection, a control circuit (CSA) 404, a control circuit (CSB) 405, a delay circuit string of the BDDA configuration (BDDA) 406, a delay circuit string of the BDDA configuration (BDDB) 407, a multiplexer 408 (MUX), which receives outputs of the delay circuit string (BDDA) 406 and the delay circuit string (BDDB) 407 for multiplexing into one output, and an output circuit (output buffer circuit) (DOB) 409. This output circuit (DOB) 409, which is an output circuit in a synchronous DRAM, also termed an SDRAM, receives a clock signal output from the multiplexer 408 (MUX) to output data (readout data) at a data output terminal (DQ) in synchronism with edges of the clock signal. The delay time tREP of the replica circuit (REP) 402 is set so as to be equal to the sum of the delay time t1 of the clock buffer 401 and the delay time t2 of the multiplexer 408 and the output circuit (DOB) 409. That is,tREP=t1+t2  (1)
Meanwhile, since the delay of the control circuit (CSA) 404 and the delay of the control circuit (CSB) 405 (delay as from a transition edge of the internal clock signal (ICLK) until the turn control signal (AFWD/ABWD) or the delay as from the output (STO) of the replica circuit 402 until the input AOA/AOB of the delay circuit strings 406 and 407 of the BDD configuration) is small as compared to the delay t1 and t2 and is not relevant to the structure and the operation of the present invention, these are disregarded in the following description.
If, in FIG. 9A, attention is directed to the phase A composed of the control circuit (CSA) 404 and the delay circuit string (BDDA) 406, the rising edge (R0) of the external clock signal (CLK) is output as a signal (ST0) through the clock buffer (CLKB) 401 (delay time=t1) and the replica circuit (REP) 402 (delay time tREP=t1+t2) so as to be output from the control circuit (CSA) 404 as a signal (AOA). This signal (AOA) is supplied to an input terminal of the delay circuit string (BDDA) 406. On selection of the phase A, the control signal (PHA) from the phase selection circuit (PHR) 403 is activated. The control circuit (CSA) 404 is supplied with the signal (ST0) from the replica circuit (REP) 402 to output the received signal as the signal AOA. The turn control signal AFWD/ABWD, output from the control circuit (CSA) 404, represents the forward direction. The edge of the clock input to the delay circuit string 406 via input terminal proceeds in one direction (rightward direction in the drawing). At a time point the clock edge has proceeded through the inside of the delay circuit string 406 a certain predetermined time by the turn control signal (AFWD/BFWD) generated in the control circuit (CSA) 404 responsive to the rising edge (R1) of the external clock signal (CLK), the proceeding direction of the clock edge is reversed. Thus, the clock edge proceeds towards left in the drawing and presents itself at an output (BOB) of the delay circuit string (BDDB) 407. The time as from the inputting of the clock edge at the input terminal of the delay circuit string 406 until a turn is equal to the time as from the turn until the outputting at the output terminal of the delay circuit string 406 (this time is indicated by [tBDD] in FIG. 9B). This represents a basic characteristic of the delay circuit string of the BDD configuration, as disclosed for example in the Japanese Patent Kokai Publication JP-A-11-66854. The edge output by the delay circuit string 406 is supplied through the multiplexer 408 (MUX) to the output circuit (DOB) 409. The output circuit (DOB) 409 then outputs data at the output terminal (DQ) in synchronism with an edge of the supplied clock edge.
The time as from the rising edge (R1) of the external clock signal (CLK) until the outputting of data from the output terminal (DQ) may be calculated to be equal toT+tBDD+t2.
On the other hand, the following equation:t1+tREP+tBDD=tCK+t1  (2)holds for the time as from the rising edge R0 of the external clock signal (CLK) until the turn at the delay circuit string 406.
If tREP=t1+t2 of the above equation (1) is taken into account, then we have:t1+tBDD+t2=tCK  (3).
That is, when the phase A is selected, the outputting of the data from the data output terminal (DQ) occurs in synchronism with the rising edge (r2) of the external clock signal (CLK).
The same applies for the operation of the phase B composed of the control circuit (CSB) 405 and the delay circuit string (BDDB) 407, such that data outputting from the data output terminal (DQ) occurs in synchronism with the rising edge (R3) of the external clock signal (CLK).
By alternately switching between the phase A and the phase B at each cycle of the external clock signal (CLK) by the control signal (PHA) and the control signal (PHB), output from the phase selection circuit (PHR) 403, data can be output from the data output terminal (DQ) in synchronism with all of the rising edges of the external clock signal (CLK).
Recently, the increasing rate in the operating speed of the DDR (Double Data Rate)-SDRAM is significant, such that the operating frequency of the entire DDR-SDRAM has come to be limited by the upper limit of the operating frequency of the BDD circuit (reciprocal of the clock period tCK).
That is, as for the delay time tBDD of the delay circuit strings 406 and 407 (time which elapses as from the inputting until the turn), in FIG. 9A, there is a lower limit tBDDmin determined by the characteristic of the delay circuit string, typically 0.3 ns to 0.5 ns and, since we have a following equationtBDD=tCK−(t1+t2)=tCK−tREP  (4)
the following condition must be satisfied:tCK>tBDDmin+tREP  (5)
For example, if tREP is 5 ns and tBDDmin is 0.5 ns, we have:tCK>5.5 ns
as a result of which, the operating frequency of the DDR-SDRAM cannot be raised to higher than about 180 MHz.
Thus, if it is desired to further raise the operating speed of the DDR-SDRAM, loaded with a delay circuit string of the BDD circuit configuration, the lower limit of the clock period tCK of the BDD delay circuit string needs to be lowered further.
In order to meet this request, there is proposed in for example the Japanese Patent Kokai Publication JP-A-11-66854 a four-phase configuration in which a phase C and a phase D are further provided in addition to the phases A and D. This configuration is shown in FIG. 10 and includes a clock buffer (CLKB) 501 which receives complementary external clock signals (CLK and /CLK) to output an internal clock signal (ICLK), a replica circuit (REP) 502 which receives the internal clock signal (ICLK), a phase selection circuit (PHR) 503 which receives the internal clock signal (ICLK) to output control signal for phase selection PHA, PHB, PHC and PHD, a control circuit (CSA) 504, a control circuit (CSB) 505, a control circuit (CSC) 506, a control circuit (CSD) 507, a delay circuit string (BDDA) 508, a delay circuit string (BDDB) 509, a delay circuit string (BDDC) 510, a delay circuit string (BDDD) 511, a multiplexer (MUX) 512 for switching between the outputs of the delay circuit string (BDDA) 508 to the delay circuit string (BDDD) 511, and an output circuit (DOB) 513, as shown in FIG. 10.
FIG. 11 is a timing diagram for illustrating the operation of the structure shown in FIG. 10. If attention is directed to the operation of the phase A, a rising edge R0 of the external clock signal (CLK) is turned around by a turn control signal AFWD/ABWD, which is generated from a rising edge R2, and data is output in synchronism with an edge R4. The same may be said of the phases B to D, that is, data may be output in synchronism with the totality of the rising edges by sequentially actuating the respective phases every CLK cycle.
As may be seen from FIG. 11, we have:tBDD=2tCK−tREP  (6)andtCK>(tBDDmin+tREP)/2  (7)so that, as compared to the configuration shown in FIG. 9, operation is possible up to ½ of the clock period tCK (that is, up to 2.75 ns in the above numerical example).